1. Field of The Invention
This invention relates to electronic devices and more particularly, to semiconductor devices having a super LSI multilayer interconnection structure.
2. Description of The Prior Art
As is known in the art, the high degree of integration of super large scale integration circuits invariably requires multilayer or multilevel interconnections where the interconnection structure has two or more layers built up therein. Semiconductor devices having such an interconnection structure include a protective layer for preventing moisture and/or impurities from entering. This protective layer is to cover the multilayer interconnection therewith and has usually a structure which includes a phosphosilicate glass layer (P-containing SiO.sub.2) and a silicon nitride film formed by plasma-enhanced CVD. A typical example of a two-layer wiring structure is illustrated with reference to FIG. 9. In the figure, there is generally shown a semiconductor device S which includes a substrate 20 having a transistor region (not shown) covered with an insulating film 21 having an opening 21a. A first metal film 22 serving as a first wiring is formed on the substrate 20 as shown. Moreover, an insulating film 23 having an opening 23a is formed over the first metal film 22 and a second metal film 24 serving as a second wiring is provided on the insulating film 23. The second metal film 24 is in contact, as C, with the first metal film 22 through the opening 23a. Finally, a protective layer 25 having a double-layered structure of a phosphosilicate glass layer and a silicon nitride layer (both not shown) is formed to cover the entire surface of the semiconductor device, thereby completing a two-layer interconnection. This interconnection structure is fundamentally composed of three lines including a line of the first wiring 22, a line of the second wiring 24 and the contact portion C where the first wiring 22 and the second wiring 24 are electrically contacted.
The degree of integration of large scale integrated circuits becomes higher with a finer size of the metal films or wirings. When an electric current is applied to such a circuit, there will arise the problem that the breakage of the fine wiring takes place. This is called electromigration (which may be hereinafter referred to often as EM) failure. This EM failure takes place due to the fact that Al atoms ordinarily used as the metal film are moved along the passage direction of electrons generated by application of the current and a portion of the film where the movement is violent is broken. To avoid this, it has been proposed that elements other than Al, e.g. Cu, Ti and the like, are added to the Al film so that the number of vacancies present in Al grain boundaries are decreased to reduce the movement of Al atoms (P. B. Gate, Solid State Technology, Vol. 3, pp. 113-120, (1983)).
Another problem involved in the fine wiring of the super large scale integrated circuits is a phenomenon where when kept merely at high temperatures, the wiring is broken. This is called stress migration (which may be often referred to as SM). With regard to the SM phenomenon, it has been reported that the breakage frequently takes place when the circuit is maintained at a temperature of approximately 150.degree. C. This will be overcome to an extent by addition of Cu or the like element (J. Kelma et al, The 22nd Annual Proceeding International Reliability Physics Symposium, pp. 1-5 (1984)).
The above two reports have been made to solve the problems on the single-layer wiring line. With LSI circuits including a double-layer or multilayer interconnection structure, the problems involved in the EM and SM phenomena at contact portions between the interconnected wirings have to be solved, like the single-layer wiring line.
Few reports have been made on the EM and SM phenomena at the contact portion. It is empirically assumed that the EM and SM characteristics will be improved by tapering the insulating film at the contact portion to improve the aluminium coverage of the second wiring. This tapered technique has now been in use. However, it has been reported that this technique has the following disadvantage (H. Tomioka et al, The 27th Annual Proceeding International Reliablility Physics Symposium, p. 57 (1989)). The second aluminium film is usually formed by sputtering at relatively high sputtering power. In this condition, when the contact portion is tapered, the substrate made generally of SiO.sub.2 is apt to be sputtered at the tapered contact portion as well. This results in SiO.sub.2 formed between the first and second aluminium films, thereby causing the EM characteristics to be degraded. Thus, care should be paid to the formation of SiO.sub.2 at the contact interface.
The status of the double-layer wiring arrangements can be summarized in the following table.
TABLE ______________________________________ Possibility for Application Prior Measure for Solving to Semiconductor Art EM Problem Device ______________________________________ EM Phenomenon first several *improved by addition of possible to use metal reports impurity elements in 1.2 .mu.m line film *improved by increas- width ing grains of Al second several *improved by addition of possible to use metal reports impurity elements in 1.2 .mu.m line film *improved by increasing width grains of Al contact few *because of poor coverage difficult to use portion reports of the second metal film in a size of at the contact portion, 1.2 .mu.m square the portion is tapered but with a problem that SiO2 is formed at the interface between the first and second metal film SM Phenomenon first several improved by addition of possible to use metal reports impurity elements in 1.2 .mu.m line film width second several improved by addition of possible to use metal reports impurity elements in 1.2 .mu.m line film width contact few *because of poor coverage not known portion reports of the second metal film, the portion is tapered, which is now under study ______________________________________
As will be apparent from the above table, although EM and SM characteristics of the first and second metal films and the problems involved in the contact portion have been individually reported, we have not found any attempt to match the respective films and the contact portion when the double-layer wiring structure is applied to semiconductor devices.